As semiconductor processing proceeds in the 10 nm technology node, a significant number of technical challenges force the use of more costly immersion layers. Some technical challenges include the minimum area requirement for critical gate pitch (3CPP), a N-P junction breakdown process margin which is much tighter in the 10 nm technology node, and corner rounding requirement (CRR) which is more critical in the 10 nm technology node. As a result of these technical challenges an immersion process for multiple layers becomes necessary. With existing processing in the 10 nm technology node, a significant reduction in process margin exists due to the impact of edge placement, compounding of CRR and required process bias.
With other existing processes, even if a well based threshold voltage (Vt) adjustment is enabled, the Vt adjustment levels still are victim to minimum area limitations prohibiting 3CPP cell swap. In other existing processes, N-P junction spacing reduction in 10 nm cells has reduced the relative breakdown margin by 33%. Due to overlay, fin placement and critical dimension (CD) tolerances, migration to immersion processing becomes necessary to recover the 33% reduction in margin. A current static random-access memory (SRAM) cell is further challenged with an additional reduction in the N-P space of almost 10%. The influence of topography, boolean comps and etch bias can further negatively impact patterning margin with tight N-P junction spacing.
A need therefore exists for methodology enabling patterning and implantation that can improve N-P junction spacing and CRR without relying on expensive immersion processes.